Programmable Clock Generators

This is idts fifth generation of programmable clock technology versaclock 5.

Programmable clock generators.

The cy22801 is a flash programmable clock generator that supports various applications in consumer and communications markets. The dynamic reconfiguration port drp interface gives system designers. The sit9105 is the industry s first 3 pll programmable clock generator with an embedded mems resonator that combines one differential and two single ended outputs. The clock generator in a motherboard is often changed by computer enthusiasts to control the speed of their cpu fsb gpu and ram.

Configurations may be stored in on chip one time programmable otp memory or changed using i2c interface. The logiclk is a programmable clock generator logicbricks ip core with twelve independent and fully configurable clock outputs. This makes them well suited for consumer data communications telecommunications and computing applications. A variety of clock generator design tools and resources are available to help simplify your clock tree design save time and reduce board space in applications such as wired communications.

Maintain signal integrity with our portfolio of low jitter clock generators with support for up to pcie gen 5 1 10gb ethernet and other industry standards. Cascade family of mems clock generators feature 4 independent frac n plls 4 inputs up to 11 outputs wide frequency range from 8 khz to 2 1 ghz and a rich set of programmable features in a small 9 x 9 mm package. While six clock outputs can be fixed by generic parameters prior to the implementation the other six clock outputs can be either fixed by generics or dynamically reconfigured in a working device. A programmable circuit for generating a clock signal is disclosed.

The device uses the cypress proprietary pll along with spread spectrum and vcxo technology to make it one of the most versatile clock synthesizers in the market. The clock generator allows for electrical configuration of various information including pll parameters input thresholds output drive levels and output. Providing highly flexible factory and i 2 c programmable lvcmos clock generators the devices feature equivalent frequency synthesis capability of up to 8 plls with exact frequency synthesis 0 ppm error significantly lower. The present invention provides a clock generator architecture that combines pll based clock generator circuitry with an on chip eprom in a monolithic clock generator chip.

Programmable clock generators also called programmable timing devices allow designers to save board space and cost by replacing crystals oscillators programmable oscillators and buffers with a single timing device.